The present invention generally relates to built in self tests for oversampled Analog to Digital converters, and more specifically relates to circuitry and a method for testing oversampled Analog to Digital converters using a state machine which simulates input levels.
Sigma delta or oversampled Analog to Digital converters sample their input signal at a high sample rate and output an averaged or low-passed filtered version of their input at a lower sample rate. Hence, for one output code of a sigma delta Analog to Digital Converter, many input samples are averaged together. The standard way to test an Analog to Digital converter is to sample a dynamic signal such as a ramp or sine wave to exercise the input signal range.
Testing Analog to Digital converters is especially important in platforms such as RapidChip, and typically requires special test hardware that adds cost to the final product. The hardware that is added typically includes a special test board and special instrumentation such as signal generators.
Some prior art methods employ on-chip signal generators. These add significant circuit overhead to the design. Prior art methods require a significant amount of additional circuitry in order to accomplish Built In Self Test.